A portfolio spanning simplified coherent modules, 200G-PON modules and high-speed optoelectronic chips.
Targeting 2–20 km AI data center and campus DCI links, our product roadmap prioritizes 3.2T+ simplified coherent modules. The SVDD self-coherent receiver requires no independent local oscillator (LO) and combines silicon photonics with photonic-electronic co-design to pursue a balance of link performance, system complexity, power and cost.
Designed for next-generation high-speed optical access networks, the module combines Stokes vector direct detection (SVDD) with silicon photonic integration to recover high-speed optical signals without an independent local oscillator at the receiver. The product plan covers integrated ONU transceiver modules and burst-mode OLT receiver modules, targeting a balance of capacity, reach, integration and deployment cost for single-wavelength 200G-class transmission.
Silicon photonic integration and high-speed analog equalization are co-designed with the optical front end and module system.
Integrates key optical functions for simplified coherent reception, supporting polarization reception and downstream electrical processing. Designed for module integration and high-speed links.
A 12-tap 4×2 MIMO FFE in analog CMOS for polarization and chromatic-dispersion compensation at the optical-module receiver, working with established IM/DD DSPs.
A high-bandwidth analog FFE performs receiver-side equalization for polarization and chromatic-dispersion compensation of dual-polarization high-speed optical signals.
Compared with all-digital equalization, the analog approach reduces digital processing load and system power while lowering chip cost and supporting domestic implementation.
Digital equalization can consume substantial power in high-speed links. Performing key equalization before the DSP reduces receiver-side digital processing pressure.
Technical exchange and R&D collaboration, shaped by real link requirements.
